Sr Principal Application Engineer - Cadence - Remote - Global
Application Engineer
Tap this card for salary charts and full compensation details.
Expand to unlock full salary context
See benchmark placement, pay-band comparison graph, and localized salary narrative.
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Key Responsibilities Hands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff, RTL to GDSII. Lead technical campaigns and strategies in the RTL to GDSII digital implementation space. Aggressively push Power, Performance, and Area (PPA) Deliver technical presentations and lead discussions internally and with customers. Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality. Support execution on critical customer flagship product tape outs. Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.
Company Information
| Location | Active listings |
|---|---|
| Remote - Global | 24 |
| Kato Scholari, Finland | 1 |
| Role type | Active listings |
|---|---|
| Software Engineer | 3 |
| Application Engineer | 3 |
| Systems Engineer | 2 |
| Product Engineer | 2 |
| Product Engineer System Verification | 1 |
| Senior Principal Design Engineer | 1 |
| Program Manager | 1 |
| Senior Principal Software Engineer | 1 |
| Lead Design Engineer | 1 |
| Emulation Design Engineer | 1 |
| Signal Integrity Engineer | 1 |
| Revenue Accounting Manager | 1 |
| Senior System Engineer | 1 |
| Technical Recruiter | 1 |
| Software Engineering Intern | 1 |
| Customer Engagement Manager | 1 |
| Scientific Software Developer | 1 |
| Legal Intern | 1 |
| Design Engineer | 1 |
| Role level | Active listings |
|---|---|
| Mid-Level | 24 |
| Senior | 1 |
Cadence appears in 25 indexed job postings in JobCrawls' Finland dataset since April 2024. In that historical index, the strongest location signals for this employer are Remote - Global and Kato Scholari, Finland.
Data shown is based on historical job postings from our database.
Job Details
Requirements
- MS degree in Computer Science/Engineering, Electrical Engineering, or related field
- 12+ years industry experience
- Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis
- Experience with IC digital implementation flows and backend EDA tools including Synthesis, Place and Route, IR Drop, design timing and power closure, RTL to GDSII
- Scripting in Perl/Tcl/Python for automation and process improvement
- Experience in floor planning and power planning for SoC designs with low power
- Experience with IC digital implementation flows and front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking
- Hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferably with CDNS tools
- Advanced clock tree synthesis techniques including SoC Clock Distribution, Clock Mesh, H-Tree
- Multiple design closure including Timing, DRC, LVS, and EMIR
- Experience with advanced technology nodes including Sub 5nm and below
- Develop, debug, and optimize design flows for SoC’s to achieve best PPA
- Strong customer-facing communication and problem-solving skills
- Continuous learning and expanding professional skillsets
- Strong verbal, written, and customer communication skills
- Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus
