Layout Design Engineer II (SerDes) - Cadence - Remote - Global
Layout Design Engineer
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Job Description
The Layout Design Engineer will be responsible for transistor-level physical layout implementation of advanced analog and mixed-signal circuits for next-generation high-speed interface IP. This role sits within the SerDes Product Team based in Cork, Ireland, and works closely with cross-functional engineering partners to deliver high-quality, manufacturable designs. Responsibilities include custom transistor-level layout for high-speed SerDes blocks, partner with circuit designers, support physical design activities, run and debug verification flows, apply advanced layout techniques, optimize for area and performance, and collaborate with cross-functional teams. Requirements include a degree in Electronic Engineering or related, hands-on experience with CMOS SERDES or high-speed I/O IC layout, knowledge of custom layout methodologies, and strong problem-solving skills. Desirable skills include PHY GDS implementation, ASIC design flow familiarity, advanced node tape-outs, scripting skills, and prior use of Cadence tools. Cadence promotes diversity and equal opportunity.
Company Information
| Location | Active listings |
|---|---|
| Remote - Global | 24 |
| Kato Scholari, Finland | 1 |
| Role type | Active listings |
|---|---|
| Software Engineer | 3 |
| Application Engineer | 3 |
| Systems Engineer | 2 |
| Product Engineer | 2 |
| Signal Integrity Engineer | 1 |
| Program Manager | 1 |
| Senior System Engineer | 1 |
| Senior Principal Software Engineer | 1 |
| Technical Recruiter | 1 |
| Emulation Design Engineer | 1 |
| Scientific Software Developer | 1 |
| Lead Design Engineer | 1 |
| Senior Principal Design Engineer | 1 |
| Legal Intern | 1 |
| Product Engineer System Verification | 1 |
| Revenue Accounting Manager | 1 |
| Customer Engagement Manager | 1 |
| Design Engineer | 1 |
| Software Engineering Intern | 1 |
| Role level | Active listings |
|---|---|
| Mid-Level | 24 |
| Senior | 1 |
Cadence appears in 25 indexed job postings in JobCrawls' Finland dataset since April 2024. In that historical index, the strongest location signals for this employer are Remote - Global and Kato Scholari, Finland.
Data shown is based on historical job postings from our database.
Job Details
Responsibilities
- Perform custom transistor-level layout for high-speed SerDes blocks, including PLLs, Clock and Data Recovery (CDR), TX/RX analog front-ends, equalisers (CTLE/DFE), bandgap and bias circuits, and high-speed clock distribution networks.
- Partner closely with analog and mixed-signal circuit designers to understand performance requirements and optimise floorplanning, parasitic-sensitive routing, signal integrity, and matching.
- Support physical design implementation activities such as floorplanning, device placement, routing, shielding and isolation, power planning, and EM/IR-aware layout practices.
- Run and debug physical verification flows, including DRC, LVS, ERC, parasitic extraction, and post-layout verification support.
- Apply advanced layout techniques such as common-centroid structures, interdigitation, symmetry constraints, guard rings, dummy fill, and matching-aware routing.
- Optimise layouts for area, yield, performance, reliability, and manufacturability.
- Collaborate with cross-functional teams including Analog Design, Digital Implementation, Packaging, Signal Integrity, and Physical Verification.
Skills & Technologies
