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ASIC Engineering Technical Leader - Cisco - Nuremberg, Germany

Posted: May 27, 2026
Posted 43 days ago
Last seen in crawl: July 7, 2026 (1d ago)
Estimated Expiry: July 1, 2026
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Role & Management
Role Level:Mid-Level
Management Tier:No People Management
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Job Description

Join Cisco’s High-Speed Optics team—an innovative group dedicated to advancing the design, integration, and validation of cutting-edge optical modules and interfaces. Our team’s work is vital to Cisco’s leadership in high-speed networking, powering the backbone of data centers and enterprise optical networks worldwide. With a diverse, highly skilled group of engineers, we foster an open, collaborative, and intellectually curious environment where every voice is valued. We are passionate about pushing boundaries, driving new technological frontiers, and shaping the future of optical communications. If you thrive in a dynamic and forward-thinking setting, you’ll find this team both inspiring and rewarding. Your Impact You will architect, design, layout, measure and productize high-speed TIA and Driver in CMOS process. You will lead efforts for a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production. You will also collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met.

Company Information

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Technology
Current open roles at Cisco on JobCrawls
LocationActive listings
Remote - Global9
Current role mix at Cisco on JobCrawls
Role typeActive listings
Account Executive3
Inside Account Executive2
Regulatory Compliance Manager1
Legal1
Technology1
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Current role-level mix at Cisco on JobCrawls
Role levelActive listings
Mid-Level8

Cisco appears in 9 indexed job postings in JobCrawls' Finland dataset since May 2025. In that historical index, the strongest location signals for this employer are Remote - Global.

Data shown is based on historical job postings from our database.

Job Details

Responsibilities

  • Architect, design, layout, measure and productize high-speed TIA and Driver in CMOS process
  • Lead efforts for a complex chip, mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production
  • Collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met
  • Define the qualification and wafer test for the designs

Requirements

  • BSEE degree with 12+ years of experience or equivalent or an MS degree with 8+ years of experience, or equivalent or a PhD with 5+ years of experience, or equivalent
  • Design, simulation and measurement of high-speed ICs such as: Transimpedance Amplifiers, Linear drivers, Programmable gain amplifiers, and equalization technics
  • Basic Analog circuits such as: Biasing circuits, voltage regulators, Opamps
1 day agoPartial Schema

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