Physical Design Engineer

Sine Engineering is seeking a Physical Design Engineer to join our team in building next-generation System-on-Chips (SoCs) from the ground up. Responsibilities include driving the physical implementation flow from synthesis through place-and-route, timing closure, and GDSII sign-off. Contribute to areas such as: Synthesis and constraint development (SDC), Floorplanning, power planning, placement, clock tree synthesis, and routing for SoC blocks and full-chip integration. Timing closure across PVT corners and operating modes, including STA, ECO planning, and sign-off. Physical verification, including DRC, LVS, ERC, antenna checks, and electromigration/IR-drop analysis. DFT integration and implementation, including scan insertion, compression, MBIST, boundary scan, and ownership of test pattern generation flows. Low-power implementation, including UPF/CPF co-design flows, power domains, level shifters, isolation, and retention strategies. Package definition and co-design, including pinout planning, bump/ball assignment, package-aware signal and power integrity, and collaboration with package and board teams. Tape-out preparation and sign-off, including GDSII generation, foundry deliverables, and DRC/LVS-clean handoff. Skills and Requirements include background in SoC physical design, RTL-to-GDSII flow knowledge, industry-standard EDA tools familiarity (Synopsys, Cadence, Siemens). Strong debugging, scripting in Tcl/Python/Perl, and proactive ownership mindset. Nice to Have experiences include package definition, mixed-signal or RF SoC, signal/power integrity, and hierarchical implementation. What We Offer covers substantial health and wellness benefits, travel coverage, and a no-crunch, high-autonomy culture. Privacy notice and GDPR compliance are noted. Apply for this Job.

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