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Monthly
€15,633 - €29,033
Posted March 1, 2026 · 160 days agoLast seen August 7, 2026Est. expiry April 5, 2026

Application Engineer

San Jose, United States
Onsite · Software Engineering
Full-time · Senior
English
No People Management
20 years experience
How this salary compares
Salary Context: Application Engineer

Hover or tap a row for full statistics (EUR / month on this chart).

Salary analysis

Compared with the selected benchmark ("Market Average: Application Engineer"), this listing's salary midpoint is about 306% higher. The offer sits above the benchmark range (€5,000–€6,000). The listed pay band (€15,633–€29,033) is wider than the benchmark, which suggests greater salary variability. This benchmark is based on 1 comparable listings.

Monthly salary comparison for Application Engineer
MarketLower bound (25th percentile)MedianUpper bound (75th percentile)
Market Average: Application Engineer€5,000/per month€5,500/per month€6,000/per month
From job ad (Senior)€15,633/per month€22,333/per month€29,033/per month
About the role

The Sr Application Engineer Architect will serve as a senior technical leader within Cadence’s North America Field Applications Team, driving strategic customer engagements and influencing next-generation EDA & Agentic-AI solutions. This role demands exceptional technical depth, proven leadership, and the ability to align cross-functional teams toward delivering advanced design solutions for leading semiconductor companies. Key Responsibilities Strategic Leadership: Define and execute technical engagement strategies for top semiconductor design team, ensuring alignment with corporate objectives and customer success metrics. Customer Advocacy: Act as a trusted advisor for executive-level stakeholders, guiding adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes (3nm and below). Team Development: Lead and mentor a high-performing team of Application Engineers, fostering technical excellence and career growth. Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements. Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure. Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader. Operational Excellence: Establish best practices for engagement models, resource planning, and technical escalations to ensure timely and successful project execution. Qualifications 20+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs. BS/MS in Electrical Engineering, Computer Engineering, or related field. Deep expertise in digital design fundamentals, advanced node implementation (3nm and below), and EDA tool ecosystems. Proven track record of leading technical teams and driving customer success at executive levels. Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure. Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders. Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and competitive solutions highly desirable.

Job Details

Responsibilities

  • Define and execute technical engagement strategies for top semiconductor design teams
  • Act as a trusted advisor for executive-level stakeholders on digital implementation and signoff technologies
  • Guide adoption of AgenticAI features across advanced nodes (3nm and below)
  • Lead and mentor a high-performing team of Application Engineers
  • Partner with R&D and Product Engineering to influence tool enhancements
  • Drive complex benchmarks, flow optimizations, and deployment of methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure
  • Represent Cadence at industry forums, author technical papers, and deliver keynote presentations
  • Establish best practices for engagement models, resource planning, and technical escalations

Requirements

  • 20+ years of experience in IC design implementation and signoff
  • Demonstrated success in managing large-scale technical programs
  • BS/MS in Electrical Engineering, Computer Engineering, or related field
  • Deep expertise in digital design fundamentals
  • Expertise in advanced node implementation (3nm and below)
  • Expertise in EDA tool ecosystems
  • Proven track record of leading technical teams and driving customer success at executive levels
  • Strong proficiency in scripting (Tcl, Python, Perl)
  • Strong proficiency in flow customization for design closure
  • Excellent communication, negotiation, and leadership skills

Skills & Technologies

TclPythonPerlGenusInnovusTempusVoltusConformalCerebrusSynthesisP&RSTAIR DropAgentic-AI
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