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Est. Monthly
Estimated €12,284 - €13,890
Posted August 7, 2026 · 1 day agoLast seen August 7, 2026Est. expiry September 11, 2026

Product Engineer

Principal Product Engineer - DIP
Shanghai, China
Onsite · Software Engineering
Full-time · Senior
English
No People Management
Bachelor
8 years experience
How this salary compares
Salary Context: Product Engineer

Hover or tap a row for full statistics (EUR / month on this chart).

Salary analysis

Compared with the selected benchmark ("All roles in Shanghai, China"), this listing's salary midpoint is about 92% lower. The offer sits below the benchmark range (€8,875–€18,049). The listed pay band (€1,024–€1,158) is tighter than the benchmark, which suggests lower salary variability. This benchmark is based on 4 comparable listings.

Monthly salary comparison for Product Engineer
MarketLower bound (25th percentile)MedianUpper bound (75th percentile)
Market Average: Product Engineer€10,128/per month€12,298/per month€14,468/per month
All roles in Shanghai, China€8,875/per month€13,087/per month€18,049/per month
Pay in our data — not quoted in ad (Senior)€1,024/per month€1,091/per month€1,158/per month
About the role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Technical Support & Case Management: Act as the primary interface for technical issues, driving resolution for complex subsystem application or implementation problems. This includes monitoring case management systems like Salesforce (SFDC) and Jira. IP Integration & Validation: Support Pre-Silicon integration, post-silicon bring-up, and verification of PHY and controller SoC integration. Conduct RTL and gate-level simulations to ensure functionality and assist with timing closure. Customer Engagement: Proactively engage with customers to identify potential issues, prioritize critical technical problems, and manage escalations, ensuring high satisfaction. Technical Leadership: Develop comprehensive knowledge bases, document product limitations, and provide feedback to internal Product Engineering and R&D teams for continuous improvement. Guidance & Training: Create and deliver technical training, seminars, and documentation to support customer success and adoption of best practices. Required Qualifications Experience: Requires 8+ years of experience in verification and design, specifically with IP development. Technical Expertise: Strong background in digital electronics, Verilog/SystemVerilog, and UVM methodology. Protocol Knowledge: Practical knowledge of memory or communication interface IP protocols such as MIPI (CSI2/DSI/I3C/PHY), PCI Express, DDR, LPDDR, HBM, or USB. Skills: Excellent debugging skills, ability to handle complex problems, and proficiency in scripting languages (TCL, Perl, or Python). Education: Bachelor’s or Master’s in Electronics or Electrical Engineering. Preferred Skills Experience with Cadence-specific tools, EDA workflows, or similar IP design platforms. Core Competencies Strong communication and presentation skills, capable of influencing both internal teams and customer stakeholders. Proactive and collaborative approach, able to work across global, cross-functional teams. Strategic thinking to drive product roadmap improvements based on user feedback. Fluent spoken English

Job Details

Responsibilities

  • Act as the primary interface for technical issues and drive resolution for complex subsystem application or implementation problems
  • Monitor case management systems like Salesforce (SFDC) and Jira
  • Support Pre-Silicon integration, post-silicon bring-up, and verification of PHY and controller SoC integration
  • Conduct RTL and gate-level simulations to ensure functionality and assist with timing closure
  • Proactively engage with customers to identify potential issues, prioritize critical technical problems, and manage escalations
  • Develop comprehensive knowledge bases and document product limitations
  • Provide feedback to internal Product Engineering and R&D teams for continuous improvement
  • Create and deliver technical training, seminars, and documentation

Requirements

  • 8+ years of experience in verification and design, specifically with IP development
  • Strong background in digital electronics, Verilog/SystemVerilog, and UVM methodology
  • Practical knowledge of memory or communication interface IP protocols (e.g., MIPI, PCI Express, DDR, LPDDR, HBM, or USB)
  • Excellent debugging skills
  • Proficiency in scripting languages (TCL, Perl, or Python)
  • Bachelor’s or Master’s in Electronics or Electrical Engineering
  • Fluent spoken English

Skills & Technologies

VerilogSystemVerilogUVMMIPIPCI ExpressDDRLPDDRHBMUSBTCLPerlPythonSalesforceJiraRTL simulationGate-level simulation

Education Level

Bachelor
Seen 20 hours agoContent Complete
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Cadence · 131 open roles
Top locations: Remote - Global · 130 · Kato Scholari, Finland · 1
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