Principal Design Engineer - Cadence - Shanghai, China

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Responsible for scheduling, designing, developing, and supporting IP models of system level memory such as SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardware based verification products. Also responsible for updating, maintaining, documenting, and supporting existing system level memory model products. Perform as individual contributor for RTL design, verification, productizing, and documentation of memory IP. Interface with internal and external customers to work on diverse problems and solutions related to emulation, simulation, or verification. Perform as team member toward cross verification of and cross training in memory IP as well as in developing and using lifecycle processes to ensure product quality. Job Requirements: The position requires MSEE, or equivalent, with a minimum of 5 years significant experience in designing complex protocols and/or hardware systems. MUST have excellent communication skills with both written and spoken English. Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows. Must excel in and demonstrate solid debugging experience/skills. Emotionally intelligent collaborator and communicator. Experience with team-wide collaboration tools and processes. Drive and ability to schedule workload and plan own tasks effectively as well as coordinate with and adapt to other's needs and priorities when needful. Agile! Adaptive! Verification experience using Cadence simulation and/or emulation products is a PLUS. Programming experience with scripting languages like Perl, TCL, C-shell is a PLUS. Experience in memory sub-system design and operation is a PLUS.