Micro-architect

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us! Role and Responsibilities As a Micro-Architect/Logic Designer, you will be responsible for leading the micro-architecture development of custom coherent interconnect IP and last level cache blocks. In this role you will be interacting with the system architects, verification, performance/power, and design implementation teams. You will be owning and driving the critical coherent interconnect related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success. This role is open to being hired at various levels, based on the individual’s background, experience, and skillset. Drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks. Partner with architects to help define next-generation Samsung coherent interconnects and LLC. Perform microarchitecture development and specification – from early high-level architectural exploration through micro architectural research and arriving at a detailed specification Work alongside the verification team to verify the functionality and correctness of the design. Collaborate with implementation to achieve your timing and area. Produce quality RTL on schedule meeting PPA goals Engage with performance and power team on achieving performance and power goals. Work with the physical design and CAD team to resolve implementation level details. Help mentor junior engineers in the team. Skills and Qualifications 6+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 4+ years of experience with a Master’s degree, or 2+ years of experience with a PhD Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs Demonstrated successful architectural through RTL design experience on high performance digital designs Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Knowledge of system caches and directory snoop filter protocols. Familiarity with different on-chip network topologies: mesh, ring, crossbar. Experience in leading and mentoring a team of engineers. Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols Knowledge of memory subsystem design including coherent cache design. Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team. Preferred candidates will possess the following: Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows. Proficient in AMBA, ACE, AXI, CHI protocols. Knowledge of coherent interconnect, memory controller, and/or cache design. Knowledge of memory subsystem, coherency, directory snoop filter protocols. Familiarity with different on-chip network topologies: mesh, ring, crossbar. Experience with a scripting language like Perl or Python.