Senior Principal Design Engineer
Hover or tap a row for full statistics (EUR / month on this chart).
Salary analysis
Compared with the selected benchmark ("All roles in Shanghai, China"), this listing's salary midpoint is about 6% lower. The offer still falls within the benchmark range (€8,102–€19,831). The listed pay band (€12,284–€13,890) is tighter than the benchmark, which suggests lower salary variability. This benchmark is based on 4 comparable listings.
| Market | Lower bound (25th percentile) | Median | Upper bound (75th percentile) |
|---|---|---|---|
| All roles in Shanghai, China | €8,102/per month | €13,087/per month | €19,831/per month |
| Pay in our data — not quoted in ad (Mid-Level) | €12,284/per month | €13,087/per month | €13,890/per month |
Responsibilities include working in Cadence Flagship Emulation and Prototyping product line; designing, developing, modifying, and productizing protocol products like PCIe, advanced Ethernet, and more, which are crucial to modern IC design and verification. The role involves logic RTL design, UVM based verification, board design/debug, and documentation. The candidate will work on complex protocol or system integration issues, electrical or timing closure, RTL design, or verification methodologies. Requirements include an MSEE or equivalent, experience in logic design and debug, RTL design with Verilog, FPGA design for Xilinx, UVM verification, and scripting languages like Perl, TCL, C-shell. Excellent communication skills are essential.
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